SERDES IP Cores
SERDES IP Cores

USB 3.0/3.1 PHY

SilabTech offers Silicon Proven USB3.1 SuperSpeed and SuperSpeedPlus PHY IP cores:

  • USB 3.1 Gen 1          5 Gbps          SuperSpeed                         in short USB3.0
  • USB 3.1 Gen 2          10 Gbps        SuperSpeedPlus                in short USB3.1

Silicon Proven USB3.1 PHY IP:

  • Lowest Power and Area available today in the market leveraging SilabTech Patented Technology
  • Available Technologies – 28nm, 40nm and 55nm and soon on 16FF
  • Support for all types of USB connectors – Type A, B and newly released Type C
  • Compliant to the latest revision of Universal Serial Bus 3.1 Specification
  • Fully integrated and verified with USB controller for complete off-the-shelf solution
  • Wire-bond and flip-chip package options are supported
  • Standard Interface with SOC – PIPE4.2, APB and IEEE1500
  • Complete Interface Solution – SERDES was integrated and tested with our partner’s Controller.

SerDes Features:

  • Support for full swing and low power swing transmitter operation.
  • 3-tap Pre/Post cursor Transmit equalization range 0 – 12db with 20mV programmability step
  • Adaptive Receiver equalization (CTLE + DFE)
  • Embedded low jitter phase-locked-loop (PLL)
  • Support for Spread Spectrum Clocking (SSC) with down-spread of 5000ppm
  • Support for Low Frequency Periodic Signaling (LFPS)
  • Crystal-less operation- can extract the Clock from Receiving data on Device side

Silicon Measurements on SMIC 40LL

Silicon Measurements for SMIC 40LL