Interface IPs

PHY IP Portfolio – USB 3.0, PCIe Gen-3, SATA 6G, MIPI D-PHY & M-PHY


  • SilabTech designs PHY and Mixed-signal IP that will be integrated into your SoC after being silicon proven by us
  • Our methodology guarantees first time right integration of our IP, because:
    • SilabTech manages SerDes, PLL and PHY in-house designs made by a highly experienced team
    • Every PHY IP is validated on our Test Chip *
    • Test Chip is characterized in our lab. Compliance Test is run for:
      • USB 3.0
      • PCIe gen-2
      • PCIe gen-3
      • SATA 6G
      • MIPI D-PHY
      • MIPI M-PHY
    • Our best-in-class technical support is offered directly by the PHY IP designers

* Supported Technologies: GlobalFoundries 28 nm and TSMC 40 nm, TSMC 28 nm

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