Silicon And Beyond MIPI PHYs are the perfect fit into Mobile Device connectivity, designs as per MIPI. ORG latest standard release and are now Silicon Proven. Those PHYs are enablers for next generation mobile device connectivity where low power consumption is at the highest priority along with great attention to Leakage power and Die area. Silicon And Beyond MIPI PHYs are used as building blocks for connectivity of high end Cameras, High Definition Displays (4K Video at 60 fps), LTE/4G Radio Modems, Memory modules, Video & Audio sources and communication with other peripheral devices.

Our Controller partners are working with us to deliver complete solution for each of the standards derivatives – FPGA boards are available to demo the complete solution.

Silicon And Beyond offer the following MIPI PHYs:

Characteristic M-PHY v3.1 D-PHY v1.2 C-PHY v1.0
Primary use case Performance driven, bidirectional packet/network oriented interface Efficient unidirectional streaming interface, with low speed in-band reverse channel Efficient unidirectional streaming interface, with low speed in-band reverse channel
HS clocking method Embedded Clock DDR Source-Sync Clock Embedded Clock
Channel compensation Equalization Data skew control relative to clock Encoding to reduce data toggle rate
Minimum configuration and pins 1 lane per direction, dual-simplex, 2 pins each (4 total) 1 lane plus clock, simplex, 4 pins 1 lane (trio), simplex, 3 pins
Maximum transmitter swing amplitude SA: 250mV (peak) LP: 1300mV (peak) LP: 1300mV (peak)
LA: 500mV (peak) HS: 360mV (peak) HS: 425mV (peak)
Data rate per lane (HS) HS-G1: 1.25, 1.45 Gb/s 80 Mbps to ~2.5 Gbps (aggregate) 80 Msym/s to 2.5 Gsym/s times 2.28 bits/sym, or max 5.7 Gbps (aggregate) per lane
HS-G2: 2.5, 2.9 Gb/s
HS-G3: 5.0, 5.8 Gb/s
(Line rates are 8b10b encoded)
Data rate per lane (LS) 10kbps – 600 Mbps < 10 Mbps < 10 Mbps
Bandwidth per Port (3 or 4 lanes) ~ 4.0 – 18.6 Gb/s (aggregate BW) Max ~10 Gbps per 4-lane port (aggregate) Max ~ 17.1 Gbps per 3-lane port (aggregate)
Typical pins per Port (3 or 4 lanes) 10 (4 lanes TX, 1 lane RX) 10 (4 lanes, 1 lane clock) 9 (3 lanes)

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