SERDES IP Cores
SERDES IP Cores

MIPI M-PHY Main Features

  • M-PHY is moving fast to become the mobile devices standard for on-board connectivity supporting wide range of auxiliaries, HD displays, modems and cameras.
  • Data rate programmable 1.248-5.830 Gbps (HS Gear 1, 2, 3)
  • Silicon Proven on GF 28 SLP
  • Support Wire Bond and Flip Chip packages
  • Support Single and Multi-lane configurations
  • MIPI.ORG Standards: CSI-3, DSI-2, UniPort-M (UniPro 1.5), DigRF v4.
  • Transmit Driver with programmable output swing 115 – 200 mVp
  • Receiver with fast-locking clock-data-recovery (CDR)
  • Embedded low jitter phase-locked-loop (PLL) with 2ps rms RJ (MPHY mask)
  • Supports PWM mode Gear 1-5 and SYS mode
  • Standard interface with SOC:
    • Protocol Interface compatible with Reference M-PHY Module Interface (RMMI) as defined in Annex A of MIPI M-Phy specification.
    • APB Interface for IP functional mode configuration
    • IEEE1500 8pin interface for DFT configuration

MIPI M-PHY Block Diagram

MIPI M-PHY Silicon Results

MIPI M-PHY Application Diagram