SERDES IP Cores
SERDES IP Cores

MIPI C+D Combo PHY

C+D Combo PHY Main features:

  1. MIPI C+DCombo PHY support upto 2.5 Gsps (Giga Symbole Per Seconds) data rate (equals to 5.7 Gbps )
  2. Operation Mode can be selected as 3x lane C-PHY or 4xData lane + 1 Clock lane DPHY
  3. D-PHY TxData Lane Type – CIL-MFAA. D-PHY Clock Lane Type – CIL-MCNN
  4. C-PHY TxLane Type – CIL-MFAA
  5. D-PHY Rx Data Lane Type – CIL-SFAA. D-PHY Clock Lane Type – CIL-SCNN
  6. C-PHY Rx Lane Type – CIL-SFAA
  7. HS & LP transmitters & LP receivers integrated
  8. Embedded Low Jitter PLL
  9. D-PHY mode supports generation of clock/data pattern which enables skew calibration for far-end HS RX
  10. D-PHY mode supports EPPI
  11. Following register programmable re-configuration supported:
    • Any physical lane could be clock lane (D-PHY mode)
    • Any physical lane could be any logical lane (D-PHY/C-PHY mode)
    • Polarity inversion (D-PHY/C-PHY mode)

Combo TX Eye Diagram: DPHY 1.5Gbps

Combo TX Eye Diagram: CPHY 2.5Gsps

For more details please contact our Sales Team.