SERDES IP Cores
SERDES IP Cores

JESD204B Sub-System

  • Complete Interface Solution of SERDES & Controller enable chip-to-chip high speed links that are silicon proven on customer SOCs.
  • Deterministic Latency across multiple lanes and up to 12.5Gbps per lane. Aligned Data from multiple data converters to a single host utilizing specific JESD204B features.
  • Continues Range and programmable date rates from 0.3Gbps up to 12.5Gbps
  • Silicon Proven on TSMC 28HPM/HPC; TSMC 55LP; GF 28SLP; GF 40LP; SMIC 40LL

Silicon Results (TX) at 12.288Gbps

  • This Interface Solution can support Single/Multi lanes configurations- Build your 100Gbps interconnect pipe with SILABTECH 8 Lane configuration.
  • SILABTECH Controller is available either as bundle along our SERDES IP or as a Stand Alone IP (Soft or Hard IP) to be used on FPGA or customer SOC.
  • Rx and Tx Controller Blocks are offered either as pair or as stand alone (unidirectional)- chose any number of Tx and Rx lanes.
  • SILABTECH interface solution supports the Physical Layer, Data Link Layer and Transport Layer.

JESD204B Controller Block Diagram- Tx and Rx

Physical Layer: Serial Lanes

  • The physical layer defines the performance of the data traansfer and electrical interfaces dominated by the SERDES, CDR and driver/receiver blocks
  • Point-to-point, unidirectional serial interface
  • AC vs. DC compliance
  • JESD204B defines 3 signal speed-grade variants
Parameter LV-OIF-Sx15 LV-OIF-6G-SR LV-OIF-11G-SR
Data Rates 312.5mbps – 3.12Gbps 312.5Mbps – 6.375Gbps 312.5Mbps – 12.5Gbps
Differential Output Voltage 500 – 1000 (mV) 400 – 750 (mV) 360 – 770 (mV)
Output Rise or Fall Time (20% – 80% into 100 load)Ω ≥ 50(ps) ≥ 30(ps) ≥ 24(ps)
Bit Error Rate (BER) ≤ 1e-12 ≤ 1e-15 ≤ 1e-15

JESD204B Interface Solution – Testchip and Evaluation Platform