SERDES IP Cores
SERDES IP Cores

DisplayPort / Embedded DP SERDES

The DP/eDP Standard was issued by VESA.ORG to address the growing need for high speed links in various digital display applications. The standard enable delivery of high definition video, audio and content protection (CP) data within one box such consumer electronic products and also between Video source and Display panels/TVs over copper cables. The SERDES is based on Differential pairs where Clock data is embedded in the signal- this standard replace the legacy LVDS IOs that had limited capacity, power issues and inter lane alignment challenges.

Silicon And Beyond DP/eDP is the VESA Compliant DP/eDP SERDES up to 8.1 Gbps per lane.

  • PHY layer IP Core includes Main link and AUX channel
  • Two variants of the standard are supported:
    • Box-to-Box DP connections with Enhanced Equalization capabilities (DP HBR 1.3)
    • Embedded connections (eDP) variant with area and power optimization for in-box, short reach channels
  • Technology – all major foundries 16/28/40nm process
  • Flip-chip package supported
  • Complete Interface Solution which is pre-integrated and tested is available (SERDES + Controller) with Industry leading Controller vendors.
  • The SERDES support Type C Connector (USB3.1 ALT Mode)

Display Port SERDES at 8.1 Gbps

Pattern: PRBS15

Eye diagram was recorded after PCB de-embedding on SMIC 40LL Chip