12.5 Gbps Multi Standard SERDES

SERDES IP Portfolio – USB 3.0, PCIe Gen-3, SATA 6G, MIPI D-PHY & M-PHY, JESD204B

SILABTECH designs PHY and SERDES IPs are ready for integration into your SoC after being silicon proven.

Our methodology guarantees first time right integration of our IP, because:

  • SILABTECH manages SerDes, PLL and PHY in-house designs made by a highly experienced team
  • Every PHY IP is validated on our Test Chip *
  • Test Chip is characterized in our lab. Compliance Test is run for:
    • JESD204B
    • USB 3.0
    • PCIe gen-2
    • PCIe gen-3
    • SATA 6G
    • MIPI D-PHY
    • MIPI M-PHY
  • Our best-in-class technical support is offered directly by the PHY IP designers

Supported Technologies: GlobalFoundries 28SLP & 40LP; TSMC 28HPM & 40LP; SMIC 40LL