0.3 – 12.5 Gbps Multi Standard SERDES

Silicon And Beyond Multi-Standard SERDES IPs are the best choice for interconnecting your SOC to its working environment and application. Designed and Verified against released Industry Standards these SERDES can be configured to operate in PC & Server applications and also in Storage, Data Networks and Industrial Applications. Silicon And Beyond all-in-one type of design enable SOC designer to define set of standards that are relevant for his application and to get COMBO SERDES in a form of ready for tape out GDS that contain only this functionality, e.g. PCIe Gen 3 + USB 3.0 + SATA Gen 3 in one SERDES IP.

Silicon And Beyond Multi-Standard SERDES IPs support wide range of protocols and speeds that are being used cross different industries and applications:

Application Standards Baud Rate
Per Lane (Gbps)
Standard Organization
PC/Servers Connectivity USB 3.0 / 3.1 5 / 10 USB Forum
PCIe Gen 1/2/3 2.5 / 5 / 8 PCI-SIG
Storage Devices SATA Gen 1/2/3 1.5 / 3 / 6 SATA
HMC- Hybrid Memory Cube 12.5 HMC Forum
Data Networks & Backplane Ethernet 1.25 IEEE
1000Base-KX 3.125/ 10.3125
10G BASE-KX4 / KR 10.3125
RAPID I/O 3.1 9.85 RapidIO.ORG
CEI-6G-SR/MR/LR 4.976 – 6.375 OIF Forum
CEI-11G-SR/LR 9.95-11.1 OIF Forum
EPON/GPON/XGPON 1.25; 2.488; 9.95  IEEE
RF & Industrial JESD204B 0.3 – 12.5 JEDEC
CPRI 1.2288 – 9.8304  CPRI
Debug HSSTP (High speed Serial Transmit Port) 1-12.5 ARM
Display Video-By-One Tx and Rx 4 Thine Elec.
DisplayPort/ eDP 1.62/ 2.7/ 5.4 / 8.1 VESA

For more details on the various SERDES technologies and Standard available please contact our Technical Experts.

Main Features:

  • Data rate programmable 0.3 -12.5Gbps
  • Silicon Proven on various Foundries and Technologies such as TSMC 28 HPM/HPC, GF 28SLP 40LP, SMIC 40LL
  • Top Class Performance- Lowest Power per Gbps and smallest footprint
  • Single or multi-lane configurations- Support Unequal number of transmit and receive lanes.
  • Wire-bond and flip-chip packages are supported
  • Transmit Driver with programmable output swing 100 – 900 mVp2p
  • Pre/Post cursor Transmit equalization range 0 – 12db with 20mV programmability step
  • Adaptive Receiver equalization (CTLE + DFE)
  • Embedded low jitter phase-locked-loop (PLL)
  • Beacon, Low-Frequency-Periodic-Signaling (LFPS), Auto-negotiation (AN) Signaling supported
  • PLL is Ring-Oscillator based- supports standard crystal generated reference clock in frequency range 12-100MHz. Phase Noise requirement for reference clock of 100MHz is -125dbc/Hz
  • Standard specific PCS layer provided with the SERDES enables standard interface with the SOC
  • Rich in DFT features (AC-JTAG, Eye-scan, Loop-back, RX Sensitivity BIST, TX level BIST, PLL BIST)

Silicon And Beyond Multi-Standard SERDES Typical Block Diagram:

Silicon Results at 6.25 Gbps and 12.5 Gbps